How to alter algorith to make ASICs obsolete? Ethash Help

cryptomined · March 30, 2018, 8:38pm

Sorry if this is not directly a ZCash related topic. But I do feel as though it would effect ZCash mining so I will post and ask here.

I believe that having both ZCash and Ethereum as decentralized as possible is very important for the crypto-eco-system. One CPU = One Vote.

Since ZCash has had plans to alter the Equihash algo to eliminate any ASIC’s… is there any advice that you could give Ethereum Developers on altering Ethash to make any ASICs in development or use obsolete?

Please see

github.com/ethereum/EIPs

EIP: Modify block mining to be ASIC resistant.

opened 05:51PM - 29 Mar 18 UTC

closed 07:08AM - 11 Jun 22 UTC

pipermerriam

> Disclaimer: My area of expertise does not lend well to me suggesting *how* to …make things ASIC resistant. I hope there are some informed opinions floating around out there who can help fill in the *how*. According to "the internet" there is an ASIC based ethereum miner on the horizon. [this *may* be the original source of that news](http://technews.cn/2018/02/12/bitmain-tsmc-dram/) If you believe the analysis in the comments on [this reddit thread](https://www.reddit.com/r/ethereum/comments/87ucsk/would_you_support_a_hard_fork_that_obsceletes_eth/) BitMain may already running these miners. I believe it is the accepted wisdom that ASIC based mining leads to increases centralization when compared to GPU mining. This leads us to two questions: 1. Should we hard fork to make ASIC mining harder and to demonstrate a willingness to hard fork any future ASIC based ethereum mining. 2. What specifically changes do we make to implement this increased ASIC resistance. ### Should we fork? I propose that people indicate support/opposition with a simple 👍 / 👎 on this main issue. I would prefer this conversation not devolve into deep discussions around this subjective topic so **my request is that people refrain from commenting on that specific question here**. ### How do we implement improved ASIC resistance This is the primary issue that I think needs to be addressed, after which we can have an informed discussion about whether we should actually do it.

Any input in the github thread would be greatly appreciated

Thank you